DVP vs MIPI CSI-2 camera interface: why the connectors don't match

A sensor module arrives with a 22-pin connector, the board has a 22-pin camera connector, they mate - and nothing enumerates. This is the most common board-level camera integration mistake, and it costs a design spin: the two connectors belong to different interfaces that share nothing but pin count. This guide explains how a DVP parallel camera interface differs from MIPI CSI-2 in signaling, clocking and protocol, why no cable converts one into the other, and which two fixes do work. You will finish able to identify what a module speaks from its pin names, size the bus you actually need, and choose between a matching host, an active bridge and a module with the right interface built in.

The decision: match the interface name, not the pin count

Read the interface line in the module's electrical specification before anything else. If it names parallel data pins D0-D7 or D[9:0], a pixel clock PCLK and sync lines such as VSYNC and HREF, the module speaks DVP. If it names a clock lane plus one to four data lanes, or says MIPI CSI-2 and D-PHY, the module speaks CSI-2. A DVP module will never enumerate on a CSI-2 port: the host's differential receivers cannot decode a single-ended parallel bus, and no packet protocol exists between the two sides. Three fixes exist: a host with a native parallel camera port, an active bridge that receives DVP and transmits USB or CSI-2, or a module that already speaks the host's interface. Everything else on this page is the evidence for that decision.

What a DVP parallel interface is

DVP moves each pixel across a bundle of single-ended lines. An 8-bit module drives D0-D7 with the pixel value; a 10-bit module adds D8 and D9. A parallel pixel clock, PCLK, marks each valid sample, and frame and line timing travel on separate sync lines written VSYNC/HREF or XHS/XVS. Register access runs over I2C, listed on many sensor sheets as SCCB. Every line is CMOS-level, typically 1.8 V or 3.3 V, so the pin count grows with bit depth and clock skew sets the reach: flat-ribbon DVP runs stay in the tens of centimetres. The interface survives because microcontroller-class hosts still ship parallel camera ports, and compact global-shutter sensors keep offering it.

What a MIPI CSI-2 interface is

CSI-2 moves the same pixels as packets over differential pairs. A clock lane runs alongside one to four data lanes; the host spreads each frame's packets across the lanes and checks a header and CRC on every packet. The electrical layer is MIPI D-PHY: low-swing differential signaling with a high-speed burst mode and a low-power control state between bursts. Lane rates run from about 80 Mb/s up to a few Gb/s per lane, set by the D-PHY generation and the link's clock configuration. Register access still runs over I2C, so the control side looks familiar even though the data side shares nothing with DVP. Because the host side is a receiver with a fixed lane count and data-type list, CSI-2 compatibility is a layered check - the MIPI CSI-2 compatibility guide walks it layer by layer. CSI-2 is also one of several embedded camera buses; the embedded interface comparison shows where it sits against GMSL2 and its peers.

Why the same pin count means nothing

Open both connectors and the similarity collapses. A CSI-2 connector spends most of its pins on ground returns interleaved between differential pairs; its signal pins are low-swing receivers. A DVP header spends its pins on single-ended data bits, one shared pixel clock and sync lines at 1.8 V or 3.3 V. Wire a DVP module to a CSI-2 header and each parallel line lands on the positive leg of a differential pair whose negative leg floats - the receiver sees an undefined level and stays silent. Wire two CSI-2 receivers together and neither side drives anything, so the result is the same silence. That second case is easy to hit, because a capture board's camera header looks exactly like a host port.

When a correctly matched CSI-2 pair still shows a black preview, the fault hides in one layer - power, clocks, lanes or packets. The layer-by-layer CSI-2 bring-up method is the structured way to isolate it.

Worked example: bus budget for a 1.2 MP global-shutter module at 60 fps

Take the case that starts most of these projects: a 1.2 MP global-shutter parallel module headed for an inspection station. The inputs: a 1280 x 960 pixel array (the standard SXGA format behind every 1.2 MP module), a 60 fps target chosen for this example, 8-bit monochrome raw output (the usual depth on parallel modules) and a 15 % blanking allowance (parallel buses carry horizontal and vertical blanking; 10-20 % is the normal planning figure).

Pixels per second: 1280 x 960 x 60 = 73,728,000 px/s, about 73.7 Mpx/s. Payload: 73.7 Mpx/s × 8 bit/px = 590 Mb/s. DVP pixel clock: one 8-bit pixel per PCLK gives 73.7 MHz; with the 15 % blanking allowance, 73.7 × 1.15 ≈ 85 MHz. CSI-2 side: one data lane in high-speed mode commonly carries about 0.8 Gb/s, so the 590 Mb/s payload fits with roughly 210 Mb/s of the lane free. At 10 bits the payload rises to 737 Mb/s, and packet headers plus CRC then consume the margin on one lane. That sets the working threshold: above about 0.7 Gb/s of payload, use two lanes.

The decision: bandwidth is not what blocks this sensor - both buses carry 590 Mb/s with room to spare. What blocks it is the physical and protocol mismatch. An 85 MHz single-ended pixel clock with eight parallel lines cannot terminate in differential receivers, and neither side speaks the other's packets. When the interface name says parallel and the port says CSI-2, stop comparing bandwidth and change the architecture: parallel host, active bridge, or a module with a native CSI-2, USB or GigE interface.

Tell what a module speaks in sixty seconds

You can classify a module without a schematic. Check the electrical specification for these tells:

• The words parallel, DVP, BT.601 or BT.656: a parallel bus; BT.656 is 8-bit parallel with embedded sync.
• Pin names D0-D9, PCLK, HREF/VSYNC or XHS/XVS: DVP.
• The words MIPI CSI-2, D-PHY or lane: CSI-2. Lane count is its own trap - why a 2-lane camera fails a 4-lane probe covers the mismatch.
• Pin names written CLK±, DATA0± or RX±: differential CSI-2 lanes.
• DP and DM beside a VBUS pin: USB, not CSI-2 - the module enumerates itself.
• UVC anywhere in the sheet: the module shows up as a standard USB video device.

The two fixes that actually work

Fix one - match the host. If the build is committed to the parallel module, put it on a host with a native parallel camera port. Microcontroller-class boards and some single-board hosts expose DVP headers, often 24-pin on a 0.5 mm pitch FPC. Confirm two numbers before ordering: the host's bus width (8-bit or 10-bit) and its maximum supported PCLK. A module whose pixel clock exceeds the host's ceiling delivers frames with torn lines.

Fix two - bridge actively. A converter board with a DVP receiver on one side and a USB or CSI-2 transmitter on the other terminates the sensor's bus and re-transmits it in the host's language. That is active silicon with its own configuration: the receiver side must match the sensor's pixel clock and sync timing, and the output side must present the data type and lane count the host expects. What a converter board must include lists the parts that separate a working bridge from a bare chip. On a CSI-2 output, the step people skip is clock-rate configuration for the bridge chip - a bridge CSI-2 clock-rate walkthrough shows what that involves. Bridging to USB is simpler for the host: the module then appears as a standard video device.

Skip the bridge: pick a module with the interface on board

If the parallel sensor was chosen for its global shutter, hold on that requirement: shutter type is independent of interface, and global-shutter sensors exist on USB3 and GigE modules. Global versus rolling shutter explains when the extra cost pays. Swapping to a module with the interface built in removes the bridge, its configuration and its failure modes from the design:

The LS-BCM-0003 is a 3.1 MP USB3 board camera with a global shutter, rated 120 fps. The MV-CB016-10GM-M-W pairs a 1.6 MP global-shutter sensor with GigE and an M12 mount. The LS-BCM-0047 is a 1.3 MP colour USB3 module with a global shutter. Each enumerates on the host with no parallel bus in the path. Filter the full board-level cameras range by interface, shutter and mount in the camera finder.

Checks before you order

• Interface, not connector: read the electrical specification's interface line and the pin names; the footprint lies.
• Lane and width match: camera lanes must not exceed host lanes; parallel hosts must match the module's 8- or 10-bit width.
• Register access: the host's I2C controller must reach the sensor's register map; without it, no sensor starts.
• Raw pipeline: a bare sensor or raw-output module hands the host unprocessed data. On hosts without an ISP, what raw sensor output means tells you what the CPU takes on.
• Power: feed any capture board or bridge from its own supply; camera headers budget power for sensor modules.
• Distance: parallel and CSI-2 ribbon runs stay in the tens of centimetres, USB reaches a few metres, and GigE reaches 100 m on a single run. If the camera rides on moving machinery, a drag-chain-rated camera data cable keeps the link alive.
• Bring-up: if the matched pair still streams black, walk power, clocks and the device tree in order - the MIPI bring-up sequence covers that path.

When the usual answer is wrong

• Your host already has a parallel camera port. Then DVP is the native, cheapest match - a bridge would add silicon, configuration and failure modes for nothing.
• You are budgeting bandwidth. At 1.2 MP and 60 fps the payload is 0.59 Gb/s; a single-lane CSI-2 host already carries it. Buying a four-lane host for a one-lane problem wastes money and pins.
• The deadline is next week. A bridge is a component with its own bring-up; for a prototype deadline, swapping to a module with a native interface usually beats configuring a bridge chip.
• The connector drove the decision. Pin count carries no protocol information: a 22-pin footprint exists on CSI-2 receivers, DVP headers and USB capture boards alike.

Next step

Decide the chain in order - module interface, host port, lanes, distance - and let the configurator do the filtering:

If the build must keep a parallel sensor, send the module's interface line to the applications team and we will confirm the matching host or bridge before you order hardware.