Linear CCD clock signals explained: phi, RS, BT and the ADC front end

You have a bare linear CCD, its datasheet, and a timing diagram dense with φ1, φ2, RS and BT pulses, plus two outputs called OS and DOS that no application circuit seems to explain. The sheet describes a finished scanner, not a bring-up. This explainer follows the charge from photodiode to ADC input: what each clock does in the transfer chain, why the two outputs exist, and the sampling scheme that turns them into one clean video signal. The rates are worked through with real numbers for a 2,160-element sensor, and the closing sections give the decision on building this front end versus buying a camera that already contains it.

A linear CCD is an analog shift register

Each pixel is a photodiode with a storage well beside it. Light fills the well with charge during integration; then a single pulse on the transfer gate empties every well at once into a shielded shift register running alongside the array. From that moment the device is an analog shift register: packets of charge sit in potential wells under a row of gates driven in two interleaved phases. While φ1 is high, packets sit under the φ1 gates; when φ2 rises after φ1 falls, every packet hops one stage toward the output. Nothing is measured inside the array. The sensor moves charge, and the single measurement happens at the end of the line.

That is why two clocks is the minimum. One phase cannot move charge in a defined direction, because it has nowhere to hand the packet. The register is also longer than the active array, with dummy elements ahead of and behind the video, which is why the first pixels out of each line are not image.

The four clocks, one job each

φ1 and φ2: walking the charge

φ1 and φ2 are non-overlapping square waves that shift the register. One element reaches the output per complete φ1–φ2 cycle pair, so the element rate, meaning pixels per second at the pin, equals the pair's full-cycle rate. If both phases go high together, adjacent wells merge and charge smears along the scan direction; the dead time between phases is not optional. Some parts add a third phase for binning: one documented sensor offers a 2-pixel summing mode outputting 1,049 pixels, driven by a φ2s clock at 75 % duty and half the frequency, merging packet pairs before the output stage.

The transfer pulse: loading a line

Once per line, a pulse on the gate between photodiodes and register loads the whole array. It must land inside the window the timing diagram draws, on two-phase parts during the φ1 interval, or charge splits between stages and the line loses contrast at one end. The pulse's period, not the register clock, sets the integration time: the array collects light from one transfer pulse to the next while the register clocks out the previous line. The two overlap by design, and that is how a scanner reads continuously.

RS: resetting the output node

RS drives the reset transistor on the output node. Before each pixel is read it dumps the node to a reference level, so every packet starts from a known baseline; without it, each pixel rides on the residue of the one before. RS fires once per element, at the element rate. Its edges also couple into the video as spikes, the artifact correlated double sampling exists to remove.

BT: the dump gate

On parts that name it BT, this gate controls the charge-dump (bleed) path from the photodiode side to a drain. Held inactive, it only sinks overflow, which is the antiblooming action: a saturated pixel bleeds off instead of flooding its neighbours. Pulsed during integration it empties the wells, making it an electronic shutter that shortens exposure without touching the readout timing. Large monolithic linear sensors use this same structure specifically for exposure control while the main timing stays fixed.

Why two outputs: OS and DOS

OS is the video output: the output node drives an on-chip source follower, and each arriving packet steps its voltage. DOS is its dummy twin, a stage electrically identical to the real output but fed no photo charge. It carries the same reset spikes, the same clock feedthrough, and the same supply and temperature drift. OS minus DOS is the clean video; OS alone is video plus everything you did not want.

Both outputs sit on a DC offset of about a volt, with some hundreds of millivolts of video swing, so neither drops straight into a 0–3.3 V ADC window: plan on AC coupling or a level shift. Treat the pair as differential from the first prototype onward. Feeding only OS to a single-ended ADC works after a fashion, but you keep every glitch the dummy output would have cancelled.

Correlated double sampling: the front end the datasheet leaves out

The standard conditioning is correlated double sampling (CDS), and it does two jobs per pixel. Sample the output just after RS, before the charge arrives: that is the reset level. Sample again after the packet has dumped onto the node: that is the signal level. Subtract. The difference removes that pixel's reset uncertainty, the RS feedthrough spike, and any drift slower than one element period.

The reset uncertainty is not a rounding error. Resetting a node capacitance C leaves kTC noise:

With k = 1.38·10⁻²³ J/K, T = 300 K and a typical 0.1 pF output node, q_n = 2.0·10⁻¹⁷ C, about 127 electrons RMS, on sensors whose full well is in the tens of thousands of electrons. CDS takes that out per pixel; averaging afterwards does not.

Two ways to build it. Analog CDS uses two sample-and-hold stages and a difference amplifier into a single-sampled ADC. Digital CDS runs the ADC at twice the element rate and subtracts in firmware or an FPGA. Below roughly 100 kS/s either is straightforward; above it, digital CDS wins, because matched sample-and-holds get expensive while converter channels keep getting less so. For anything beyond a bench bring-up, plan on digital CDS. A component-level walk-through of the same chain on a compact sensor is in the knowledgebase article on solving linear CCD timing and ADC constraints.

Worked example: 2,160 elements at 200 lines per second

The case: a scanner-class prototype inspecting a 210 mm wide web with a 2,160-element sensor, the array size common in fax and flatbed machines, at 200 lines per second.

Inputs:

• Active elements: 2,160, from the sensor.
• Dummy lead-in: 32 element cycles before the first valid pixel, the dead-cycle figure scanner-class timing notes give after the transfer pulse ends.
• Line rate: 200 Hz, the design target. Across 210 mm, 2,160 elements give 210 / 2,160 = 97 μm per pixel, about 261 dpi; the matching scan speed is 200 × 97 μm = 19.4 mm/s.

Rates, top down:

• Elements per line: 2,160 + 32 = 2,192.
• Element rate: 200 × 2,192 = 438,400 Hz, so t_e = 1 / 438,400 = 2.28 μs.
• φ1 and φ2: one pulse of each per element period, so both at 438 kHz, non-overlapping, near 45 % duty.
• RS: 438 kHz, one pulse per element, between pixels.
• ADC: 2 × 438,400 = 876,800 samples/s for digital CDS. A 1 MS/s converter covers it with 14 % margin; anything slower cannot sample every pixel twice.

Data leaving the front end: 438,400 samples/s × 12 bit = 5.3 Mbit/s, about 0.5 % of a GigE link. The pipe is never the problem at these rates; the analog path is.

The one ratio to confirm against your own sheet is elements per clock cycle: classic two-phase scanner parts deliver one element per φ1–φ2 cycle pair. If yours divides a master clock differently, every rate above scales by that ratio and nothing else changes. On a moving web, slave the line rate to an encoder instead of holding 200 Hz; encoder-triggered line scan capture: wiring quadrature inputs covers that side.

The line scan camera line rate calculator does the speed-to-line-rate step in one pass when the web speed is what you know.

Timing rules the datasheet assumes you know

• Non-overlap is absolute. Both phases high at once merges wells and smears charge along the scan direction.
• One RS per element, aligned between pixels. A missing RS leaves stair-stepping video; a doubled one resets mid-pixel.
• Budget the dummies. The first valid pixel arrives about 32 cycles after the transfer pulse. A constant column offset in the rebuilt image is a miscounted dummy budget, not a sensor fault. When a whole channel dies instead, the troubleshooting walkthrough of an all-pixel output fault on a three-channel linear CCD is the right template.
• Exposure lives on the transfer pulse. If lines saturate at full rate, pulse BT to cut integration rather than dropping lines or slowing the web.
• Bring-up order. Rails and bias first, clocks second.

Generating the pulses is its own task. For clocking from a DAQ card, driving a linear image sensor with a DAQ card clock and trigger covers routing, levels and trigger wiring.

Build the front end or buy the camera

Everything above, the clocks, the CDS, the ADC, the dummy management, already lives inside every finished line scan camera. You receive corrected digital pixels over GigE or Camera Link, and the setup question becomes line rate and optics rather than reset spikes: how to set the line rate of a line scan camera is that half of the job.

The decision:

• Build when you need unusual timing, direct access to raw video, a one-off experiment, or an array you already own. The cost is your time, one differential-input ADC and a clean clock source.
• Buy when the system must run unattended, when you need TDI, colour or calibrated gain, or when pixel rates pass about 1 MS/s and the front end stops being a weekend project.

The LS-LCM-0016 is a 2K GigE camera with 7 μm pixels, a 58 kHz line rate, TDI and an M42 mount. That line rate is 290 times the 200 Hz of the worked example, from a front end that is already debugged. For colour, the MV-CL042-91GC-V2 is the 4K step with 7 μm pixels, GigE and a 29 mm image circle. For wide, fast webs the LS-LCM-0099 is 8K on 10GigE with an M72 mount.

Values as printed in each product's data sheet; open a part for its drawing and full specifications.

The sensors inside modern cameras are CMOS, with per-column CDS on chip and no external front end at all; the trade-offs are laid out in CCD vs CMOS sensor differences, and the output structures are compared across monochrome and colour line scan camera sensor types. Whatever camera you pick still needs a capture path: Camera Link frame grabber compatibility for line scan and the frame grabbers category cover it, and the camera finder or the camera step of the system configurator will pair the pieces.

Checks before you order anything

• Scope OS and DOS with the sensor covered: both flat, close in DC level, clean RS spikes. A stuck rail is a front-end fault, not optics.
• Write the elements-per-clock ratio from the timing diagram into the rate math before picking the ADC.
• Budget the dummy lead-in, 32 cycles typical, into line length and any image reconstruction offset.
• Match the ADC input range to the outputs' offset and swing, and decide AC coupling versus level shift now.
• Measure non-overlap on the clock generator with a scope; do not trust the code's intent.
• If buying instead: confirm the lens mount and image circle cover the line length at the sensor format, then match the grabber interface before anything else.