Generate negative analog sync pulses for a CCIR camera from a DAQ card

A CCIR analog camera switched to external sync does not take a logic pulse. It wants negative-going drive: H-sync at 15.625 kHz and V-sync at 50 Hz, each swinging from a 0 V baseline down to a negative level set by the camera's drive circuit. A DAQ card's digital outputs toggle between 0 and 5 V, so no code trick makes them fit. This guide gives you the standard timing, the buffer arithmetic at 4 MS/s, a level-shift circuit for unipolar outputs, the wiring, and the checks that prove the camera has locked.

Are CCIR sync pulses digital or analog?

They are analog: each pulse swings from a 0 V baseline down to a negative drive level, measured on a scope at the camera connector, so any output that only produces logic levels cannot reproduce them.

A scope shows the pulses looking square, but the two states sit at 0 V and below ground. The amplitude comes from the camera's drive circuit rather than from any logic family. That combination — negative polarity plus a camera-set amplitude — is what rules out counter outputs and digital lines, and it points the job at the analog output channels.

CCIR fixes the rates instead: 625 lines per frame at 25 frames per second works out to 15,625 lines per second, the 15.625 kHz line rate. 2:1 interlacing splits the frame into 50 fields of 312.5 lines, one every 20 ms. The edges themselves are fast, so the update rate of the output channel still matters; the buffer arithmetic below sizes it at 4 MS/s.

Why can't a digital output drive them?

Because a digital line's two states are 0 V and 5 V while this camera needs 0 V and a negative level. The shape matches; the reference and amplitude do not. No setting inside the card moves a TTL output below ground.

Counter and pulse-train outputs carry the same limit; they are logic signals by design. The clean route is the analog output channels: select a bipolar range such as ±5 V, write the negative samples directly, and no external hardware exists to miswire. The fallback — a digital line feeding an inverting stage — belongs to cards with unipolar outputs only, and it is covered further down.

This article synthesizes the sync itself. If your camera instead takes one external trigger per frame from a photoelectric sensor or PLC, wire and time that case with the analog camera external trigger synchronization guide; different signal, same discipline of scoping before you trust the link.

What timing and levels must the pulses meet?

CCIR fixes the rates — 15,625 lines per second, so a 64 µs line period, and 50 fields per second, so a 20 ms field period, interlaced into 25 frames. The oscilloscope fixes the amplitudes and the pulse widths. On a typical CCIR board camera you will measure H-sync at 0 V to −2.7 V and V-sync at 0 V to −2 V; confirm both on your own unit before you write a single buffer sample.

Composite video's line sync is 4.7 µs wide by the standard, and board-camera H-drive outputs land close to that value, so the example starts there. The V-drive width is camera-specific: the example assumes 2 ms and the verification step replaces that number with whatever your scope shows.

Because a field is 312.5 lines, the V pulse lands half a line off the H grid on alternate fields. That offset is normal CCIR interlace, and it is the reason both channels must update from one shared sample clock: two independent clocks let the half-line relationship drift, and the interlace jitters with it.

Before building anything, check which external mode the camera's sync selector offers — separate H and V drive versus composite sync. The wiring below drives separate H and V inputs; a camera limited to composite input needs the full composite sync waveform, which a two-level H and V build does not reproduce.

How do you generate both syncs from one analog output task?

Build one frame-long buffer per channel, start a single analog output task with both channels sharing one sample clock, and switch regeneration on so the card replays the buffers continuously — H-sync 625 times and V-sync twice per 40 ms frame, with no code in the loop.

1. Scope the camera's own sync outputs. Run the camera on internal sync and record H and V amplitudes and widths from the scope; expect values close to the table above.
2. Choose the update rate so one line is a whole number of samples; the next section works 4 MS/s through the arithmetic.
3. Build two arrays, one per channel, each one frame long: baseline samples at 0 V, pulse samples at the measured levels, widths rounded to whole samples.
4. Create one task with both channels on a single sample clock and enable regeneration, so the card replays the buffers without new writes from the host. The shared clock is what keeps the half-line interlace offset exact.
5. Wire the outputs through the level-shift stage if you need one, then the cable, and scope at the camera connector: 0 V baseline, negative peaks, the widths you rounded.
6. Move the camera's sync selector to external and run the lock checks in the verification section below.

How many samples does each buffer need?

At a 4 MS/s update rate the arithmetic lands on whole numbers: one 64 µs line is 256 samples, a 4.7 µs H pulse rounds to 19 samples (4.75 µs), one 40 ms frame is 160,000 samples, and the 2 ms V pulse assumed here is 8,000 samples.

Worked example, arithmetic in the open:

• Sample interval: 1 ÷ 4,000,000 Hz = 0.25 µs per sample.
• Samples per line: 64 µs ÷ 0.25 µs = 256.
• H pulse: 4.7 µs ÷ 0.25 µs = 18.8, rounded to 19 samples = 19 × 0.25 µs = 4.75 µs, which is 0.05 µs wide of the target, about 1 %.
• Lines per frame: 40 ms ÷ 64 µs = 625 exactly, so the H pattern repeats 625 times per buffer with no leftover samples.
• Buffer length per channel: 625 × 256 = 160,000 samples (the same number as 40 ms ÷ 0.25 µs).
• V pulse: 2 ms ÷ 0.25 µs = 8,000 samples, once per field of 80,000 samples (20 ms ÷ 0.25 µs), twice per buffer.
• Buffer memory: 160,000 samples × 2 channels × 2 bytes = 640 kB, held once and regenerated.

If your card tops out below 4 MS/s, any rate that divides 64 µs into whole samples works: 2 MS/s gives 128 samples per line and a 0.5 µs quantum, so the 4.7 µs pulse rounds to 9 samples, or 4.5 µs. Re-scope after rounding, because the width error is now 0.2 µs. If 640 kB exceeds the card's on-board output memory, use the driver's host-memory regeneration mode where it exists, or stream the buffers continuously through a doubled buffer.

What if the analog output cannot go below 0 V?

Add one inverting stage: divide the 5 V logic pulse down to +2.72 V with 4.7 kΩ over 5.6 kΩ, then invert at unity gain with an op-amp running from a negative rail. The camera sees the 0 to −2.7 V drive it expects.

The divider arithmetic: 5 V × 5.6 kΩ ÷ (4.7 kΩ + 5.6 kΩ) = 2.72 V, and the unity-gain inverter turns that into −2.72 V, within 1 % of the target. Repeat the stage for V-sync with the divider aimed at 2 V: 3.6 kΩ over 2.4 kΩ gives 5 V × 2.4 ÷ 6.0 = 2.00 V, inverted to −2.00 V. Power the op-amp from split rails — ±5 V from a small DC-DC module is enough — because a single positive rail cannot swing below ground any more than the card could.

Bipolar analog outputs (±5 V and ±10 V ranges are common) make this section unnecessary: write the negative samples and be done. The stage exists for cards with unipolar 0-to-5 V outputs, or for a digital line whose timing you like but whose levels you must fix outside.

One number picks the op-amp: the sync input's current draw. At a high-impedance input of 10 kΩ, the H-sync swing draws 2.7 V ÷ 10 kΩ = 0.27 mA, which any general-purpose op-amp drives. At a 75 Ω video-style input it draws 2.7 V ÷ 75 Ω = 36 mA, which needs a line-driver-grade part or an added buffer stage.

Which cable carries the pulses to the camera?

A low-rate sync pair is easy cable work: any shielded cable with open leads at the driver end does the job electrically. At 15.625 kHz the cable's length and capacitance sit nowhere near a limit, and grounding and shielding decide the result.

Cameras that bring sync out on an M8 round connector are the case for the LS-CBL-0300, an M8 8-pin male-to-open-end cable with eight cores over 7 m, rated for drag-chain use. Put H-sync, V-sync and the common reference on three of the eight cores and cap the rest.

Where the sync input sits behind a DB9 — capture devices and I/O breakouts often have one — the LS-CBL-0224 runs a DB9 female to open leads over 7 m, and the solder-up is the same three signals.

Tie the analog-output ground and the camera's sync ground together at one point and carry that reference through the cable, rather than counting on mains earth. A missing common reference produces pulses that look right on the bench scope yet never arrive at the camera — exactly the failure mode in the camera trigger common reference article, and the most common cause of a scope-everything, camera-ignores-it afternoon.

An analog camera prints cable noise into the picture as lines and bars; the analog camera image split in two case was a cable fault, and the same discipline keeps injected sync clean. Keep the sync run away from motor and power wiring and land the shield at one end.

How do you verify the camera has locked?

Scope at the camera connector first — 0 V baseline, negative peaks at the amplitudes you measured, the widths you rounded — then move the sync selector to external and judge the picture: a locked CCIR image holds steady frame to frame, with no vertical roll and no line tear.

A locked camera frames a moving target identically every frame; a free-running one lets the target drift or the field relation flip. Pull the sync cable for a second: on most board cameras the picture snaps to internal-clock timing, and reconnecting snaps it back. That swap is your proof the external sync, not luck, is running the scan.

If the capture side reports no video once you switch modes, work through the source checks in the frame grabber video source article: wrong video standard, wrong termination or a dead sync path each stop detection.

No scope on the bench? Route each sync line into a spare analog input and record a few milliseconds of it. Input channels that only read positive volts clip the pulses flat at zero, and the negative voltage conversion fix for analog input cards covers converting that negative-going signal so the plot shows the real waveform.

When should you not drive sync from a DAQ at all?

When one camera runs at its own pace, leave it on internal sync: the internal crystal needs no wiring, cannot underrun and never drifts against itself, so external drive only earns its keep when the scan must line up with something else.

Reach for DAQ-generated sync in three cases: event or strobe timing that must catch a specific line or field; two or more analog cameras that must scan in phase; and capture hardware that needs the camera's timing locked to the rest of the cell. Anything less, and the rig adds two failure modes — a stalled output task and a level-shift stage — to maintain forever.

For digital cameras the same job moved onto the trigger line, and its timing arithmetic is in the camera hardware trigger frame rate article. If you are still choosing the camera itself, the analog vs digital camera comparison sets out where analog scan control still wins.

For the parts side, the camera cables range holds the open-ended leads, the accessories finder filters them by connector and length, and the system configurator pairs camera, capture and cabling in one pass. More trigger and timing work lives on the systems topic page, and if your camera's sync input is undocumented, the contact page is the way to reach us with scope plots.